UlaCache: Unified Logical Addressing for Sparse LLM Serving

Long contexts increase the memory cost of the key-value (KV) cache in large language model (LLM) inference.

Sparse attention reduces attention computation and memory traffic by selecting historical tokens, but the retained KV cache must remain available for later decoding steps.

We present UlaCache, a KV cache management system built around a unified logical address space spanning GPU KV pools and optional CPU memory.

Stable logical references let the inference engine allocate and select KV independently of physical placement.

Common allocation and sparse-access interfaces support data-parallel (DP) and tensor-parallel (TP) attention.

For distributed storage, local GPU buffers retain selected KV across decoding steps, so only missing entries require transfers.

When CPU storage is enabled, Parallel Bucketed LRU (PB-LRU) manages a GPU pool shared across requests. It updates recency metadata and selects eviction victims in parallel.

UlaCache transfers KV and then updates the address mappings.

With speculative decoding enabled under matched CPU and GPU memory budgets, UlaCache achieves peak decoding throughput speedups of 1.16 $\times$ (DP) and 1.70 $\times$ (TP) on H200, and 1.73 $\times$ (DP) and 2.51 $\times$ (TP) on B300, compared with the state-of-the-art baseline.